Semiconductor chip laminate and manufacturing method thereof



PROBLEM TO BE SOLVED: To provide a semiconductor chip laminate in which a part of an end of an upper layer semiconductor chip protrudes toward a side beyond an end of a lower layer semiconductor chip and the deformation of the upper layer semiconductor chip is suppressed to prevent inclination of the upper layer semiconductor chip. SOLUTION: The semiconductor chip laminate 1 is provided with a substrate or a first semiconductor chip 2 and second and third semiconductor chips 3, 4. At least a part of an end 4a of the third semiconductor chip 4 protrudes in the side beyond the end 3a of the second semiconductor chip 3. A supporting layer 9 is formed between the bottom surface of a protruding portion 4A of the third semiconductor chip 4 and the top surface of the substrate or the top surface of the first semiconductor chip 2. The supporting layer 9 includes particles 10 for regulating a gap between the first and third semiconductor chips 2 and 4. COPYRIGHT: (C)2008,JPO&INPIT
【課題】上層の半導体チップの端部の少なくとも一部が下層の半導体チップの端部よりも側方に張り出している半導体チップ積層体であって、上層の半導体チップの変形が抑制されており、上層の半導体チップが傾くことが防がれている半導体チップ積層体を提供する。 【解決手段】基板もしくは第1の半導体チップ2と、第2、第3の半導体チップ3、4とを備え、第3の半導体チップ4の端部4aの少なくとも一部が第2の半導体チップ3の端部3aよりも側方に張り出しており、第3の半導体チップ4の張り出している部分4Aの下面と、基板の上面もしくは第1の半導体チップ2の上面との間に支持層9が充填されており、該支持層9が第1、第3の半導体チップ2、4の間隔を規制する粒子10を含む、半導体チップ積層体1。 【選択図】図1




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    US-8362624-B2January 29, 2013Samsung Electronics Co., Ltd.Multi-chip package and method of manufacturing thereof
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